Flash memory, which is sometimes called “flash ROM”, is a type of non-volatile memory that can be erased and reprogrammed in units of memory called blocks. It is a variation of electrically erasable programmable read-only memory which, unlike flash memory, is erased and rewritten at the byte level, which is slower than flash memory updating. Flash memory is used in digital cellular phones, digital cameras, LAN switches, PC Cards for notebook computers, digital set-up boxes, embedded controllers, and other devices.
Flash memory gets its name from the organization of the microchip, which allows a section of the memory cells to be erased in a single action or “flash”. Flash memory uses higher voltages than most other types of memory cells. A conventional semiconductor memory device containing flash memory cells at the core of the device also contains periphery transistors that can handle and supply the higher voltage needed for the core flash memory cells. The periphery transistors have a lightly doped drain (LDD) region implanted in the substrate and then a sidewall is formed and a higher doped source/drain region is formed behind the LDD in order to handle the higher voltages needed. As the dosage in the higher dose source/drain region becomes higher, a wider spacer is needed. A wider spacer impacts the size requirements for the ever-decreasing semiconductor device configuration.
Prior Art FIG. 1A illustrates the basic configuration of a conventional periphery transistor 100a with a design channel length 170 and effective channel length 175. Substrate 105 contains a grown layer of gate oxide 130 and a layer comprising a polysilicon floating gate 110. After an LDD region 140 is implanted into substrate 105, a sidewall spacer 120 is deposited and a higher doped source/drain region 150 is implanted. When voltage is applied, current 160 flows from source to drain.
Prior Art FIG. 1B Illustrates a conventional periphery transistor 100b with a design channel length 170 and an effective channel length 185 in which the higher doped source/drain region 150 is diffused past the LDD 140 region and under the gate 110 area. When high voltage is applied in this instance, current 160 may flow through substrate 105 rather than flowing from source to drain. The memory cell 100b thus may become inoperable. This malfunction is referred to as a current breakdown.
Another problem that may occur when the source/drain region 150 diffuses under the gate 110 area is known as short channel effect. Design channel length 170 is measured from one edge of polysilicon gate 110 to the other, but effective channel length 175 of Prior Art FIGS. 1A and 185 of Prior Art FIG. 1B is approximately the distance from one inner edge of the LDD 140 and/or source/drain region 150 to the other inner edge, whichever is shortest. Threshold voltage is a function of effective channel length as shown in Prior Art FIG. 2A. If effective channel length varies substantially from design channel length, the threshold voltage may be out of specification, causing a malfunction of the transistor. For example, if the design threshold voltage is between lower limit 210 and upper limit 220 of FIG. 2A, it is possible that transistor 100a of FIG. 1A would perform optimally at point 215 on curve 200a. However, if source/drain 150 were diffused under LDD 140 as shown in FIG. 1B, the threshold voltage may drop to point 205 on curve 200a of FIG. 2A. This could put the threshold out of spec and cause a malfunction of transistor 100b.
As the state-of-the-art semiconductor devices become increasingly smaller, the conventional process for forming the silicon nitride layer that forms a common source area coupled to a source region of a transistor and the sidewalls at the drain region may become inadequate. Presently, the source and drain regions of periphery transistors are formed simultaneously with the source and drain of the aforementioned core memory cell. Requirements for sidewall spacer width at the periphery transistors may begin to impact the formation of a contact at the drain region of the core memory cell as the semiconductor devices decrease in size.
Thus, what is needed is a method for fabricating a semiconductor device that allows for adequate space at the core memory cell drain to form a contact and that reduces diffusion of the source and drain regions and shortening of channel length, thereby reducing malfunctions and improving performance in periphery transistors and core flash memory cells of the conventional semiconductor devices.